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ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 1 features ? peak efficiency up to 94.5 % at 12vin to 1.8vout, 93.3 % at 1.2v out ? 40 a powirstage ? includes: integrated d river, control mosfet, s ynchronous mosfet and schottky d iode ? < 1ua disable d icc bias current ? <500ua enabled icc bias current ? input voltage (vin) range of 4.5v to 17 v with available 14:1 vin_div monitor pin ? flexible drive voltage (vdrv) from 4.5v to 13.2v to optimize converter efficiency ? integrated bootstrap pfet for impro ved high side mosfet enhancement ? vdrv under voltage lockout protection ? 5v vcc with under voltage lockout protection ? switching frequency up to 1.5 mhz ? over - temperature tfault alert flag with internal temperature exceeds 150 c ? mode pin s electable 3.3v tri - state pwm logic or ir active tri - level (atl) pwm logic ? efficient dual sided cooling ? small 4mm x 6 mm x 0.9mm pqfn package ? lead- free rohs compliant package applications ? high current solutions with true sleep requirements ? high frequency, low profile dc- dc converters ? voltage regulators for cpus, gpus, and ddr memory arrays description the ir3552 int egrated powirs tage? contains a low quiescent current synchronous buck gate dr iver ic which is co - packed with control and synchronous mosfets and low side schottky diode to further improve efficiency . the package is optimized for pcb layout, heat transfer , driver/mosfet control timing , and minimal switch node ringing when layout guidelines are followed . the paired gate driver and mosfet combinatio n enables higher efficiency at lower output voltages required by cutting edge cpu , gpu and ddr memory designs. the ir3552 also supports <1ua disabled icc bias current when the enable pin is pulled low. this feature supports ultra - low or ?near - off? power shutdown requirements of battery powered devices. 1. 5 mhz switching frequency enables high performance transient response, allowing miniaturization of output inductors, as well as input and output capacitors while maintaining industry leading efficiency. t he ir3552 ?s superior efficiency enables smallest size and lower solution cost. the ir3552 provides two selectable pwm logic modes, the regular 3.3v tri - state pwm logic or international rectifier?s active tri - level (atl) pwm logic. the atl pwm logic elimin ates a dedicated body - brakin g tm pin and improves the transient response of the converter during load release. the ir3552 provides a thermal warning output set to 150c, which makes it possible to protect critical circuits on the pcb. ordering information base part number package type standard pack orderable part number form quantity ir3552 m trpbf pqfn 4 mm x 6 mm tape and reel 3 000 ir3552 mtrpbf
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 2 pinout diagram figure 1: ir3552 top view functional block dia gram figure 2 : block diagram pgnd gatel vdrv pgnd vcc pgnd vin vin boost vin 1 2 5 3 4 6 16 15 12 13 14 7 11 9 8 10 22 18 20 21 17 19 23 mode pwm lgnd en nc tfault vin _ div pin 25 gatel sw pin 24 pgnd tfault vin_div pwm 6 7 8 9 10 11 14 15 16 vin vin vin sw sw sw sw sw sw 24 12 13 pgnd pgnd pgnd 3 boost power-on reset (por), 3.3v reference, fault detection and shoot through control 22 mode 23 vcc 1 en 20 5 25 gatel gatel driver driver 18 2 21 lgnd 22 3.3v 4 pgnd 18k ir3552 vdrv vdrv vin /14 vin lgnd lgnd vcc & vdrv uvlo, temperature sensing lgnd 500k 25k
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 3 typ ical application figure 3 : one phase voltage regulator in standard pwm mode figure 4 : one phase voltage regulator in ir atl mode sw pwm vin pgnd en vdrv mode vdrv boost vin mode tfault lgnd en pwm vin _ div vin _ div csin + csin - ir 3552 4 . 5 v to 13 . 2 v 4 . 5 v to 17 v c 2 10 uf x 2 c 6 0 . 22 uf c 3 1 uf c 5 0 . 22 uf r 2 2 . 49 k l 1 150 nh 2 14 - 16 3 21 23 22 17 20 18 12 , 13 , 24 6 - 11 c 1 0 . 22 uf pgnd 4 vout c 8 470 uf c 7 22 uf tfault vcc vcc 5 v gate drivers with shoot through control , and fault detection 1 c 4 0 . 1 uf sw pwm vin pgnd en vdrv mode vdrv boost vin mode tfault lgnd en pwm vin _ div vin _ div csin + csin - ir 3552 4 . 5 v to 13 . 2 v 4 . 5 v to 17 v c 2 10 uf x 2 c 6 0 . 22 uf c 3 1 uf c 5 0 . 22 uf r 2 2 . 49 k l 1 150 nh 2 14 - 16 3 21 23 22 17 20 18 12 , 13 , 24 6 - 11 c 1 0 . 22 uf pgnd 4 vout c 8 470 uf c 7 22 uf tfault vcc vcc 5 v gate drivers with shoot through control , and fault detection 1 c 4 0 . 1 uf
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 4 pin descriptions pin # pin name pin description 1 vcc connect this pin to a +5v bias supply. place a 0.1uf high quality low esr ceramic capacitor from this pin to the lgnd pin. 2 vdrv connect this pin to a sep arate supply voltage between 5v and 12v to vary the drive voltage on both control and synchronous mosfets. place a 1uf high quality low esr ceramic capacitor from this pin to gnd. note that on the control mosfet , the gate drive voltage is vdrv less the bootstrap diode voltage drop. 3 boost floating bootstrap supply pin for the upper gate drive. connect the bootstrap capaci tor between this pin and the sw pin. the bootstrap capacitor provides the charge to turn on the control mosfet. connect a 0.22 uf capacitor from boost to sw pin. 4, 12, 13 , 24 pgnd high current power g round. note all pads are internally connected in the package. p rovide low resistance connections to the ground plane and respective output capacitors. 5, 25 gatel gate connection of the synchronous mosfet. 6 - 11 sw high current switch n ode output. 14- 16 vin high current input supply pads. provide low resistance connections to the supply rail. ensure proper bypass capacitor values and layouts to the pgnd pads. 17 vin_div output containing divided vin analog information, (vin - lgnd)/14 with respect to lgnd. the internal resistor divider is disconnected from vin when en is low. an active pull - down is provided for phase fault communication. 18 tfault over temperature fault output. tfault will pull to 3.3v when the driver exceeds 150 o c and will remain high until 130 o c. it has a 25k it has a 500k
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 5 absolute maximum rat ings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. pin number pin name v max v min i source i sink 1 vcc 6 .5 v - 0.3v na 10ma 2 vdrv 15v - 0.3v na 1a for 100ns, 100ma dc 3 boost 15v with respect to sw, 35v with respect to pgnd - 0.3v with respect to sw 1a for 100ns, 100ma dc 2 a for 100ns, 100ma dc 4, 12, 13, 24 pgnd 0.3v - 0.3v 20a rms 45a rms 5, 25 gatel 15v with respect to pgnd - 5v for <200ns, - 0.3v dc with respect to pgnd 2a for <100ns, 200ma dc 4a for <100ns, 200ma dc 6 -11 sw 25v - 5v for 10 0ns, 25v for 100ns, - 0.3v dc 45a rms 20a rms 14-16 vin 25v - 0.3v 10 a rms 20 a rms 17 vin_div vcc + 0.3v - 0.3v 1ma 20ma 18 tfault vcc + 0.3v - 0.3v 5 ma 1ma 20 en vcc + 0.3v - 0.3v 1ma 1 ma 21 lgnd 0 v 0 v 5 0ma 1ma 22 pwm vcc + 0.3v - 0.3v 5 ma 1ma 23 mode vcc + 0.3v - 0.3v 1 ma 1ma thermal information thermal resistance, junction to top ( jc_top ) 23.3 c/w thermal resistance, junction to pcb ( pin 1 7) ( jb ) 2.4 c/w thermal resistance ( ja ) 1 21.7 c/w maximum operating junction temperature - 40c to 150c maximum storage temperature range - 65c to 150c esd rating hbm class 1b , jesd22 - a114f standard cdm class iii, jesd22 - c101 standard msl rating 3 reflow temperature 260c note: 1. thermal resistance ( ja ) is measured with the component mounted on a high effective thermal conductivity test board in free air. refer to international rectifier application note an - 994 for details.
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 6 electrical specifica tions the electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. typical values represent the median values, which are related to 25c. recommended operatin g conditions for rel iable operation with margin parameter symbol min max unit recommended vin range vin 4.5 1 7 v recommended vcc range vcc 4.5 5.5 v recommended vdrv range vdrv 4.5 13.2 v recommended switching frequency ? sw 200 1500 khz recommended operating junction temperature t j -40 125 c electrical character istics parameter symbol conditions min typ max unit efficiency powirstage peak efficiency note 2 vin=12v, vout=1.2v, ? sw = 300khz, l=22 0nh , 0.2 9 m, vdrv =6.8v, no heat sink, no air flow. 93. 3 % vin=12v, vout=1.2v, ? sw = 400khz, l=150nh 0.29m, vdrv =6.8v, no heat sink, no air flow. 92. 6 % pwm input standard tri - state mode ( figure 5 ) pwm input rising threshold v ih(c_pwm) 2.4 1 2.55 2. 7 5 v pwm input falling threshold v il(c_pwm) 0.75 0.82 0.89 v tri - state lo_gate threshold v trilothresh 0.95 1.03 1.10 v tri - state lo_gate hysteresis v trilohyst - 200 - mv tri - state hi_gate threshold v trihithresh 2.21 2.35 2.48 v tri - state hi_gate hysteresis v trihihyst - 200 - mv tri - state hold off time t trihold - 4 0 - ns pwm input pull - up voltage v pwm_pull up pwm input floating - 1.60 - v pwm input resistance r pwm pwm input floating - 3.75 - k? minimum recognized pwm pulse width minpwm atl (ir) and tri - state modes - 20 - ns pwm active tri - level (atl) mode (figure 6 ) pwm input high threshold v ih(c_pwm) 0.95 1.03 1.10 v pwm input low threshold v il(c_pwm) 0.75 0.82 0.89 v pwm tri - level high threshold v tl(c_pwm) 2.4 1 2.55 2. 75 v pwm tri - level low threshold v th(c_pwm) 2.21 2.35 2.48 v pwm input current low i c_pwmlow v pwm = 0v - - 82 - ua pwm input current mid i c_pwmmid v pwm = 1.8v - - 500 - ua
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 7 parameter symbol conditions min typ max unit pwm input current high i c_pwmhigh v pwm = 2.7v - - 1 - ma minimum recognized pwm pulse width minpwm ir atl and tri - state modes - 20 - ns vindiv divider ratio vdiv (vin - lgnd)/vindiv - 14 - v/v vindiv total divider resistance r vindiv - 462 - k? fault pull down resistance vin_div fault - 300 - ohm enable input ? en input voltage high v en_h 1.15 2 2.7 v input voltage low v en_l 0. 54 0.8 1.2 v input resistance r en referenced to lgnd - 500 - k? thermal warning - tfault output over temperature threshold ot - 150 - c over temperature hysteresis ot hys - - 20 - c tfault source current v(tfault)=2.4v 0.45 1 .5 5 ma tfault output high voltage 2.4 3 .2 3.6 v input resistance r tflt referenced to lgnd - 25 - k? bootstrap diode forward voltage bd fv i(boost) = 35ma - 595 - mv vcc & vdrv under voltage lockout vcc rising threshold for por v ccrise - 3.90 4.20 v vcc falling threshold for por v ccfall - 3.40 - v vdrv rising threshold for por v drvrise - 3.80 4.20 v vdrv falling threshold for por v drvfall - 3.35 - v general supply bias current off i vcc + i vdrv en=0v - 0.6 5 ua vdrv supply bias current i drv400k f pwm = 400khz, 10% duty cycle, vdrv=5v - 12.5 - ma i drv5v pwm float - 85 - ua i drv12v pwm float - 140 - ua vcc supply bias current i vccatl atl pwm mode, pwm float 0.2 0.48 1.2 ma i vcctri tri - state pwm mode, pwm float 0.2 0.43 1.2 ma notes 1. guaranteed by design but not tested in production 2. applies to ir3552 4mm x 6mm package on ir approved pcb layout. controller loss and inductor loss are not included.
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 8 pwm timing diagram figure 5 : ir3552 timing when c onfigured in 3.3v tri - state standard pwm m ode figure 6 : ir3552 t iming diagram when c onfigured in ir atl pwm m ode pwm sw gatel normal pwm tri - state tri - state v pwm _ high v pwm _ low v pwm _ tri normal pwm gatel pwm normal pwm atl tri - state atl tri - state normal pwm v atl _ high v atl _ low v atl _ tri _ high v atl _ tri _ low sw
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 9 typical operating ch aracteristics circuit of figure 31 , v in =12v, v out =1.2v, ? sw = 400khz, l=150nh (0.29m), pwm mode, vcc= 5v, vdrv=7v, t ambient = 25c, no heat sink, no air flow, 8 - layer pcb board of 3.7?(l) x 2.6?(w), no pwm controller loss, no inductor loss, unless specified otherwise. figure 7: typical ir3552 efficiency , 300khz figure 8: typical ir3552 efficiency , 400khz figure 9 : typical ir3552 power loss , 400khz figure 10: normalized power loss vs. input voltage figure 11 : normalized power loss vs. output voltage figure 1 2 : normalized power loss vs. switching frequency
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 10 typical o perating characteris tics circuit of figure 3 , v in =12v, v out =1.2v, ? sw = 400khz, l=150nh (0.29m), pwm mode, vcc= 5v, vdrv=7v, t ambient = 25c, no heat sink, no air flow, 8 - layer pcb board of 3.7?(l) x 2.6?(w), no pwm controller loss, no inductor loss, unless specified otherwise. figure 1 3 : normalized power loss vs. vdrv voltage (circuit of figure 31) figure 14: normalized power loss vs. output inductor (circuit of figure 31) figure 15: thermal derating curve figure 16 : vcc current in tristate figure 17: vcc current vs. switching frequency figure 18 : vdrv current vs. switching frequency
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 11 typical o perating characteris tics circuit of figure 3 , v in =12v, v out =1.2v, ? sw = 400khz, l=150nh (0.29m), pwm mode, vcc= 5v, vdrv=7v, t ambient = 25c, no heat sink, no air flow, 8 - layer pcb board of 3.7?(l) x 2.6?(w), no pwm controller loss, no inductor loss, unless specified otherwise. figure 19: switching waveform in standard pwm mode, 0a figure 20 : switching waveform in standard pwm mode, 4 0a figure 21: switching waveform in ir atlpwm mode, 0a (circuit of figure 4) figure 22 : pwm to switching delay in pwm mode, 10a figure 23 : tristate delay in pwm mode, 10a figure 24 : tristate delay in pwm mode , 10a
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 12 typical operating ch aracteristics circuit of figure 3 , v in =12v, v out =1.2v, ? sw = 400khz, l=150nh (0.29m), pwm mode, vcc= 5v, vdrv=7v, t ambient = 25c, no heat sink, no air flow, 8 - layer pcb board of 3.7?(l) x 2.6?(w), no pwm controller loss, no inductor loss, unless specified otherwise. figure 25 : pwm to switching delay in ir atl mode, 10a (circuit of figure 4) figure 26 : tristate delay in ir atlmode, 10a (circuit of figure 4) figure 27 : tristate delay in ir atlmode, 10a (circuit of figure 4) figure 28 : enable (en) delay, 0a figure 29 : enable (en) delay, 0a figure 30 : vin to vin_div rati o
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 13 general description the ir3552 contains a high - efficiency and high speed mo sfet driver optimized to drive a pair of integrated control and synchronous n - channel mosfets up to 1.5mhz. the patented ir active tri - level (atl) feature allows complete enable and disable control of both mosfet pairs thr ough the pwm input signal from the controller. the timing and voltage leve ls of atl are shown in figure 6 . during normal operation the pwm transitions between low and high voltage levels to drive the synchronous and control mosfets. the pwm signal falling edge transition to a low voltage threshold initiates the high - side driver turn off after a short propagation delay. the dead time control circuit monitors the internal high gate signals and respective sw voltages to ensur e the control mosfet is turned off before turning on the synchronous mosfet. the pwm rising edge transition through the high - side turn on threshold initiates the turn off of the synchronour mosfet after a small propagation delay. the adaptive dead time circuit provides the appropriate de ad time by determining if the synchronous mosfet gate voltage has cross ed the lower threshold before allowing the high gate voltage to rise and turn on the control mosfet. theory of operation power - on reset (por) the ir3552 incorporates a power - on reset protection . this ensures that both the high - and low - side output drivers are active only after the device supply voltage v cc and v drv both have exceeded a certain minimum operating threshold. the v cc and v drv supplies are monitored and both the drivers are set to the low state, hold ing both external mosfets off. once both vcc and vdrv cross the rising por threshold and if the ir3552 is in ir atl mode, the outputs are held in the low state until a transition from tri - state to active operation is detected at the pwm input. for standar tri - state pwm mode, the por operation is the same except the driver does not look for an input tri - state before functionin g . during normal operation the drivers continue to remain active until v cc or vdrv fall below their respective falling por thresholds . integrated bootstrap pfet the ir3552 features an integrated bootstrap pfet to reduce external component count. this enab les the ir3552 to be used effectively in cost and space sensitive designs. the bootstrap circuit is used to establish the high side mosfet gate driver bias voltage and consists of a pfet (which includes a body diode in parallel ) and an external capacitor c onnected betwe en the sw and boo s t pins . the external bootstrap capacitor is charged through the pfet when the sw node is low . standard pwm tristate mode if the mode pin is grounded, the ir3552 accepts regular three - level 3.3v pwm input s ignals. as shown in figure 5 , when pwm input is above v pwm_high , the synchronous mosfet is turned off and the control mosfet is turned on. when pwm input is below v pwm_low , the control mosfet is turned off and synchronous mosfet is turned on. if pwm pin is floated, the built - in resistors pull the pwm pin into a tri - state region centered around 1.6v. ir active tri - level (atl) pwm inpu t signal when the mode pin is tied to vcc, t he ir3552 gate drivers are driven by a patented tri - level pwm control signal prov ided by the ir digital pwm controllers , as shown in figure 4 . during normal operation, the rising and falling edges of the pwm signal transition between 0v and 1.8v to control pulse width modulation of the integrated mosfets . to force both mosfets off s imu ltaneously, the pwm signal crosses a tri - state voltage level higher than the tri - state high threshold. this threshold based tri - state results in a very fast disable for both the mosfet pairs with only a small tri - state propagation delay. mosfet switching r esumes when the pwm signal falls below the tri - state threshold into the normal operating voltage range. this fast tri - state operation eliminates the need for any tri - state hold - off time of the pwm signal to dwell in the shutdown window. dedicated disable or
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 14 enable pins are not required which simplifies the routing and layout in applications with a limited number of board layers. it also provides switching free of shoot - through for slow pwm transition times of up to 20ns. the ir3552 is therefore tolerant of stray capacitance on the pwm signal lines. the ir3552 provides a pull - up bias current to drive the pwm input to the tri - state condition of 3.3v when the pwm controller output is in its high impedance state. multi - level pull - up currents are designed to dri ve worst case stray capacitances and allows for pwm transition s into the tri - state condition rapidly to avoid a prolonged period of mosfet conduction during faults. the pull - up currents are disabled once the pwm pin exceeds the tri - state threshold to conserve power. start up in ir atl mode during initial startup in ir atl mode , the ir3552 holds both high - and low - side mosfets off, even after por threshold s are reached . this mode is maintained while the pwm signal is pulled to the tri - state threshold l evel greater than the tri - state high threshold and until it transitions out of tri - state. it is this initial transition out of the tri - state which enables both drivers to switch based on the normal pwm voltage levels. this startup configuration also ensur es that any undetermined pwm signal levels from a controller in pre - por state will not result in high - or low - side mosfet turn on until the controller is out of its por. for tri - state mode, the por operation is the same except the driver does not look for an input tri - state before functioning . high - side driver each high - side driver controls an in ternal floating n - channel mosfet which can be switched at 1 .5 mhz. the external bootstrap boo s t pin capacitor referenced to the sw node is used to bias the in ternal mosfet gate. when the sw node is at ground, the boot strap capacitor is charged to the supply voltage using the boo s t pfet and this stored charge is used to bias the internal mosfet when the pwm signal goes high. once the high - side mosfet is turned on, the sw voltage is driven to the vin supply voltage and the boo s t pin voltage is equal to vin plus the vdrv voltage (note: without any diode voltage drop) . when the pwm signal goe s low, the high side mosfet is turned off by pulling the gate to the sw voltage. low - side driver the ir3552 low - side driver is designed to drive the in ternal n - channel mosfet to frequencies of 1 .5 mhz. the low - side driver is biased from the vdrv supply volt age to turn the mosfet on . when the low - side mosfet is turned on the sw node is pulled to ground. this allows re charging of the boot strap capacitor for the next high - side mosfet drive event . adaptive dead time a djustment in a synchronous buck configuration care should be taken to prevent both high and low side mosfets from being on simultaneously. such an event could result in very large shoot - through currents and could lead to long term degradation of the power stage. a fixed dead time does not provide o ptimal performance due to variations in converter duty cycles , bias voltages and temperature . the ir3552 provides an adaptive dead time adjustment to minimize dead time to an optimum duration which allows for maximum efficiency. the ?break before make? ad aptive design is achieved by monitoring gate and sw voltages to determine the on or off status of a mosfet. adaptive dead time also provides zero - voltage switching (zvs) of the low - side mosfet with minimum current conduction through its body - diode. when operating in ir atl mode , the pwm input switches bet ween 1.8v and 0v . the pwm falling edge transition turns off the high - side mosfet and turns on the low - side mosfet. the adaptive dead time circuit ensure s the internal high side mosfet vgs is below 1.25v and the sw node voltage is below 1.38v before the low side mosfet is turned on. the pwm rising edge transition turns off the low - side mosfet and turns on the high - side mosfet. the adaptive dead time circuit ensure s the internal low side mosfet vgs is belo w 1.25v before the high side mosfet is turned on.
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 15 frequency range the ir3552 is designed to operate over a wide frequency range. the lower limit of the output frequency range is dictated by the size of the boo s t capacitor which provide s bias to the high - s ide mosfet driver during the entire on - time. the upper limit of frequency is determined by thermal limitations as well as pulse width limitations. the ir3552 is designed to operate with output frequencies as low as 20 0khz and in excess of 1 .5 mhz . enable t he ir3552 has its own enable input (en). respective high and low mosfets are held off while en is low. this allows for low quiescent current operat ion, which is required for next generation portable devices to improve battery life. the ir3552 is ready to accept pwm activity in less than 10usec after the part is enabled via en. overtemperature aler t the ir3552 provides an over - temperature alert signal, tfault. this signal will pull to 3.3v when the temperature of the device reaches 150 o c. the s ignal will then be cleared when the temperature has reduced to 130 o c. application informat ion figure 3 s how s a typical single phase, high density application circuit for the ir3552 with tristate standard pwm mode . configuring the pwm mode t he pwm mode is programmed using the mode pin. a high on this pin sets ir atl mode. a low sets standard 3.3v tri - state mode. the mode selection pin is latched into the ir3552 at power up and during en cycling and cannot be changed after these events. power loss calculati on the single - phase ir355 2 efficiency and power loss measureme nt circuit is shown in figure 3 1 . sw vin pgnd vcc boost pwm csin + csin - lgnd tfault en vin _ div ir 3552 vdrv v in v out c 2 47 uf x 4 c 5 0 . 22 uf c 4 0 . 22 uf r 2 2 . 49 k l 1 150 nh c 6 470 uf x 3 c 1 0 . 22 uf vcc i vcc i in i out c 3 0 . 1 uf c 7 1 uf v sw mode vdrv i drv figure 3 1 : ir355 2 power loss measurement the ir 3552 power loss is determined by, vdrv drv vcc cc in in loss i v i v i v p + + = out sw i v ? = = vcc=7v, t ambient = 25c, no heat sink, and no air flow. the efficiency of an interleaved multiphase ir355 2 converter is always higher than that of a single - phase under the sam e conditions due to the reduced input rms current and more input/output capacitors. the measured single - phase ir355 2 power loss under the same co nditions is provided in figure 9 . if any of the application condition, i.e. input voltage, output voltage, swi tching frequency, vcc mosfet driver voltage or inductance, is different from those of figure 9 , a set of normalized power loss curves should be used. obtain the normalizing factors from figure 10 to figure 14 for the new application conditions; multiply th ese factors by the p ower loss obtained from figure 9 for the required load current.
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 16 as an example, the power loss calculation procedures under different conditions, v in =10v, v out =1v, ? sw = 5 00khz, vcc=5v, l= 170 nh, vcc=5v, i out =30a, t ambient = 25c, no heat sink, and no air flow, are as follows. 1) determine the power loss at 30a under the default test conditions of v in =12v, v out =1.2v, ? sw = 400khz, l=150nh, vcc=7v, t ambient = 25c, no heat sink, and no air flow. it is 4. 3 w from figure 9 . 2) determine the input voltage normalizing factor with v in =10v, which is 1.0 based on the dashed lines in figure 10. 3) determine the output voltage normalizing factor with v out =1v, which is 0.9 2 based on the dashed lines in figure 11. 4) determine the switch ing frequency normalizing factor with ? sw = 5 00khz, which is 1.035 based on the dashed lines in figure 12. 5) determine the mosfet drive voltage normalizing factor with v drv =5v, which is 1. 22 based on the dashed lines in figure 13. 6) determine the induct a nce normalizing factor with l= 17 0nh, which is 0.9 85 based on the dashed lines in figure 14. 7) multiply the power loss under the default conditions by the five normalizing factors to obtain the power loss under the new conditions, which is 4. 3 w x 1.02 x 0 .90 x 0.99 x 1.18 x 0.94 = 4. 8 w. thermal derating figure 15 shows the ir 355 2 thermal derating curve with the case temperature controlled at or below 125c. the test conditions are v in =12v, v out =1.2v, ? sw =400khz, l=150nh (0.29m), vcc=7v, t ambient = 0c to 90c, no heat sink, and airflow = 0lfm / 100lfm / 200lfm / 400lfm. if any of the application condition, i.e. input voltage, output voltage, switching frequency, vdrv mosfet driver voltage, or inductance is different from those of figure 15 , a set of ir 355 2 case temperature adjustment curves should be used. obtain the temperature deltas from figure 10 to figure 14 for the new application conditions; sum these deltas and then subtract from the ir 355 2 case temperature obtained from figure 9 for the r equired load current. 8) from figure 15 , determine the highest ambient temperature at the required load current under the default conditions, which is 66c at 30a with 0lfm airflow and the ir 355 2 case temperature of 125c. 9) determine the case temperatur e with v in =10v, which is +0 .0 based on the dashed lines in figure 10. 10) determine the case temperature with v out =1v, which is - 2.4 based on the dashed lines in figure 11. 11) determine the case temperature with ? sw = 5 00khz, w hich is +1.1 based on the dashed lines in figure 12. 12) determine the case temperature with v drv = 5v, which is + 6.5 based on the dashed lines in figure 13. 13) determine the case temperature with l= 170 nh, which is - 0.4 based on the dashed lines in figure 14. 14) sum the case temperature ad justment from 9) to 13), +0. 0 - 2.4 +1.1 + 6. 5 - 0.4 = + 4 .8. deduct the delta from the highest ambient te mperature in step 8), 66c ? (+ 4 .8c) = 6 1 .2c. boot strap circuit the integrated boot strap pfet of the ir3552 reduces the external component count, cost and space. the bootstrap capacitor cboot stores the charge and provides the voltage required to drive the external high - side mosfet gate. a minimum 0.1uf capacitor value is recommended with a provisional series r esistor in case pcb layouts or operating environments need a slower switch node rise time. supply d ecoupling c apacitor vcc decoupling to the ir3552 is provided by a 0.1uf bypass capacitor c vcc located close to the supply input pin. a series resistor rvcc, typically 10, is added in series with the supply voltage to filter high fr equency ringing and noise. a 1 uf capacitor is recommended for the vdrv decoupling capacitor, cdrv .
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 17 pcb layout c onsiderations pcb layout and design is important to driver performa nce in voltage regulator circuits due to the high current slew rate (di/dt) during mosfet switching. ? locate all power components in each phase as close to each other as practically possible in order to minimize parasitics and losses, allowing for reasonabl e airflow. ? input supply decoupling and bootstrap capacitors should be physically located close to their respective ic pins. ? high current paths like the gate driver traces should be as wide and short as practically possible. ? the ground connection of the ic should be as close as possible to the low - side mosfet source. ? use of a copper plane under and around the ic and thermal vias to connect to buried copper layers improves the thermal performance substantially. * contact international rectifier for a layout example suitable for your specific application.
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 18 metal and component placement ? lead land width should be equal to nominal part lead width. the minimum lead to lead vsdflqj vkrxog eh ? pp wr suhyhqw sho rting. ? lead land length should be equal to maximum part lead length +0.15 - 0.3 mm outboard extension and 0 to + 0.05mm inboard extension. the outboard extension ensures a large and visible toe fillet, and the inboard extension will accommodate any part m isalignment and ensure a fillet. ? center pad land length and width should be equal to maximum part pad length and width. ? only 0.30mm diameter via shall be placed in the area of the power pad lands and connected to power planes to minimize the noise effec t on the ic and to improve thermal performance. figure 3 2 : ir355 2 metal and component placement 23 16 17 18 19 20 21 22 25 24 5 4 3 2 1 11 10 9 8 15 14 13 12 7 6
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 19 solder resist ? the solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. the solder resist miss - alignment is a maximum of 0.05mm and it is recommended that the low power signal lead lands are all non solder mask defined (nsmd). therefore pulling the s/r 0.06mm will always ensure s nsmd pads. ? the minimum solder resist width is 0.13mm typical. ? at the inside corner of the solder resist where t he lead land groups meet, it is recommended to provide a fillet so a solder uhvlvwzlgwkri?ppuhpdlqv ? the power land pads vin, pgnd, and sw should be solder mask defined (smd). ? ensure that the solder resist in - between the ohdgodqgvdqgwkhsdgodqglv?ppgxh to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. figure 3 3 : ir355 2 solder resist
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 20 stencil design ? the stencil apertures for the lead lands should be approximately 65% to 75% of the area of the lead lands depending on stencil thickness. reducing the amount of solder deposited will minimize the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. ? the low power signal stencil lead land apertures should therefore be shortened in length to keep area ratio of 65% to 75% while centered on lead land. ? the power pads vin, pgnd and sw, land pad apertures should be approximately 65% to 75% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open. solder paste on large pads is broken down into small sections with a minimum gap of 0.2mm between allowing for out - gassing during solder reflow. ? the maximum length and width of the land pa d stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. figure 3 4 : ir355 2 st encil design * contact international rectifier to receive an electronic pcb library file in cadence allegro or cad dxf/dwg format.
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 21 marking information figure 3 5 : pqfn 4mm x 6 mm 3552m ?ywwp xxxx part # assembler(?)/date(yw w)/lead - free indicator(p) code lot code pin 1
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 22 package information figure 36 : pqfn 4mm x 6 mm
ir35 52 40a integrated powirstage ? www.irf.com | ? 201 4 international rectif ier february 19, 2014 | final 23 data and specifications subject to change without notice. this product will be designed and qualified for the industrial market. qualification standards can be found on ir?s web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 - 7105 tac fax: (310) 252 - 7903 visit us at www.irf.com for sales contact information . www.irf.com

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